Calendar
IEEE Boston Course Information (hosted by MITRE Corporation)
This is a Hybrid Course
Lecturer: Kendall Farnham (Dartmouth College)
Time: 6:00PM – 7:30PM
Course Overview:
Field-programmable gate arrays (FPGAs) are versatile integrated circuits that offer a flexible and reconfigurable hardware platform for implementing custom digital circuits, particularly in applications requiring specialized architectures. Unlike application-specific integrated circuits (ASICs), FPGAs can be programmed and reprogrammed after manufacturing using hardware description languages (HDLs), enabling rapid prototyping and iterative design processes. FPGAs can be found in telecommunications, signal processing, aerospace, and other scenarios demanding high-performance computing, parallel processing, low-latency data processing, and real-time operations. The newest trends include integrating FPGAs with systems on chip (SoCs) for implementing low-latency machine learning (ML) and artificial intelligence.
This Advanced Digital Design course is an intensive program designed to build upon foundational concepts in digital logic design and equip students with the skills needed to implement robust high-speed ML algorithms on an FPGA. Through a combination of theoretical lectures, hands-on exercises, and practical projects, students will explore advanced FPGA topics encompassing architectural considerations, signal integrity, timing analysis, and optimization techniques to achieve reliable and efficient high-speed designs. Additionally, this course will encourage students to explore current research papers and real-world industry applications to foster a deeper appreciation for advancements in state-of-the-art FPGA design.
Target audience: Students and professionals with a base knowledge of FPGA design looking to advance hardware design skills for developing complex customized circuits for efficient implementation of ML.
Benefits of attending:
- Valuable professional development creating skills that lead to job offers
- Reinforce and expand knowledge of VHDL and FPGA-specific design methodology.
- Develop skills for implementing high-speed, robust, reliable circuits on FPGAs.
- Gain understanding of real-world industry applications of FPGAs and SoCs.
Course Objectives: By the end of this course, students will possess the expertise needed to tackle complex high-speed hardware design challenges using FPGAs. They will be well-prepared to contribute to cutting-edge research, industry projects, and advancements in areas such as telecommunications, data centers, embedded systems, and high-performance computing.
Prerequisites:
- Understanding of digital logic design principles and methodology (e.g., Boolean algebra, finite state machines, data path elements)
- Familiarity with VHDL programming (or Verilog)
- Experience with FPGA development boards and tools (e.g., Vivado)
Speaker Bio:
Kendall Farnham (Dartmouth College)
Kendall Farnham is a PhD candidate in Dr. Ryan Halter’s bioimpedance lab at the Thayer School of Engineering, Dartmouth College. She has 10+ years of experience in the electrical and computer engineering (ECE) field and 5+ years of teaching and mentoring experience, having held several leadership positions within academia and industry. She received her bachelor’s degree in ECE in 2014, worked in the defense industry as a software engineer for 4 years where she discovered her passion for research, and returned to school to expand her education to include hardware design for space medicine applications. Specifically, she is interested in FPGA-based biomedical device design, currently working to develop space-compatible technologies that use impedance to monitor and detect physiological effects of space travel. Her expertise includes high-performance FPGA-based digital system design, analog circuit design, multi-modal imaging algorithms, and system integration.
Detailed Course Outline:
- Review of Digital Logic Design and FPGA Programming
- Boolean algebra, combinational and sequential circuits, finite state machines
- FPGA, SoC, and SoM architectures and toolchains
- VHDL programming techniques and design methodology
- Writing effective testbenches, RTL simulation in Vivado
- Introduction to ML algorithms and FPGA-specific optimization strategies
- High-throughput Communication on FPGAs
- Pipelining and parallelism for high-speed designs
- Synchronous vs. asynchronous communication protocols (SPI, SCI, UART, LVDS, I2C, PCIe, USB, Ethernet, etc.)
- Compare hardware/software/firmware implementations of ML: throughput speeds, resource utilization, and latency
- Methods used to achieve ultra-high sampling rates (>> system clock, GS/s range)
- Utilizing advanced IP cores and IO buffers for high-speed interfaces and data storage
- Advanced FPGA Techniques for High-speed Systems
- Clock domain crossing verification and synchronization techniques
- Resource utilization, critical path identification, and optimization strategies
- Timing constraints, static and dynamic timing analysis
- Signal integrity analysis
- High-Speed Design Verification and Testing
- Simulation-based verification techniques, advanced debugging, and waveform analysis
- Post-layout verification and back-annotation
- Test and validation strategies for high-speed designs
- Utilizing debug cores for real-time logic analysis
- Machine Learning on FPGAs
- Algorithm validation and verification in software
- Compare capabilities and implementation strategies of ML on FPGAs, SoCs, and SoMs
- Optimization strategies for efficient ML implementation in hardware (e.g., convolution)
- Digital Systems in Industry
- Techniques and best practices for scalable, reusable, reliable, and robust FPGA design
- Board-level considerations for high-speed signals: PCB layout guidelines, power distribution and decoupling, transmission line theory and termination techniques
- Emerging trends for FPGA-based digital signal processing (DSP) applications
REGISTRATION FEES:
Early Rate ends on September 3, 2024
IEEE Members Early Rate: $120.00
IEEE Non-Members Early Rate: $250.00
Rates after September 3, 2024:
IEEE Members: $140.00
IEEE Non-Members: $300.00
Decision to run the course is: Monday, September 9, 2024
We can offer Continuing Education Units (CEU) and Professional Development Hours (PDH), if requested. A small fee may apply for the credits.
Course Format: Live Webinar, 4.0 hours of instruction!
IEEE Members Early Rate: $95
IEEE Members Rate after October 1: $110
Non-Members Early Rate: $115
Non-Member Rate after October 1: $130
Decision (Run/Cancel) Date for this Course is Friday, October 18, 2024
Reference book: “Neural Networks and Deep Learning” by Michael Nielsen, http://
This Part 1 and the planned Part 2 (to be confirmed) series of courses will teach many of the core concepts behind neural networks and deep learning.
More from the book introduction: “We’ll learn the core principles behind neural networks and deep learning by attacking a concrete problem: the problem of teaching a computer to recognize handwritten digits. …it can be solved pretty well using a simple neural network, with just a few tens of lines of code, and no special libraries.”
“But you don’t need to be a professional programmer.”
The code provided is in Python, which even if you don’t program in Python, should be easy to understand with just a little effort.
Benefits of attending the series:
- Learn the core principles behind neural networks and deep learning
- See a simple Python program that solves a concrete problem: teaching a computer to recognize a handwritten digit
- Improve the result through incorporating more and more core ideas about neural networks and deep learning
- Understand the theory, with worked-out proofs of fundamental equations of backpropagation for those interested
- Run straightforward Python demo code example
The demo Python program (updated from version provided in the book) can be downloaded from the speaker’s GitHub account. The demo program is run in a Docker container that runs on your Mac, Windows, or Linux personal computer; we plan to provide instructions on doing that in advance of the class.
(That would be one good reason to register early if you plan to attend, in order that you can receive the straightforward instructions and leave yourself with plenty of time to prepare the Git and Docker software that are widely used among software professionals.)
Course Background and Content: This is a live instructor-led introductory course on Neural Networks and Deep Learning. It is planned to be a two-part series of courses. The first course is complete by itself and covers a feedforward neural network (but not convolutional neural network in Part 1). It will be a pre-requisite for the planned Part 2 second course. The class material is mostly from the highly-regarded and free online book “Neural Networks and Deep Learning” by Michael Nielsen, plus additional material such as some proofs of fundamental equations not provided in the book.
Outline:
- Feedforward Neural Networks
- Simple (Python) Network to classify a handwritten digit
- Learning with Stochastic Gradient Descent
- How the backpropagation algorithm work
- Improving the way neural networks learn:
-
- Cross-entropy cost function
- SoftMax activation function and log-likelihood cost function
- Rectified Linear Unit
- Overfitting and Regularization:
-
- L2 regularization
- Dropout
- Artificially expanding data set
Pre-requisites: There is some heavier mathematics in learning the four fundamental equations behind backpropagation, so a basic familiarity with multivariable calculus and matrix algebra is expected, but nothing advanced is required. (The backpropagation equations can be also just accepted without bothering with the proofs since the provided Python code for the simple network just make use of the equations.) Basic familiarity with Python or similar computer language.
Speaker Background: CL Kim works in Software Engineering at CarGurus, Inc. He has graduate degrees in Business Administration and in Computer and Information Science from the University of Pennsylvania. He had previously taught for a few years the well-rated IEEE Boston Section class on introduction to the Android platform and API.
The 37th IEEE Workshop on Signal Processing Systems (SiPS) is a premier international forum in the area of design and implementation of signal processing systems. It addresses all aspects of architecture and design methods of these systems. Emphasis is on current and future challenges in research and
development in both academia and industry.
Important Dates:
Technical Papers: 03 April 2024
Paper Notifications: 26 June 2024
Special Session Proposals: 31 July 2024
Tutorial Proposals: 31 July 2024
The 37th IEEE Workshop on Signal Processing Systems (SiPS) is a premier international forum in the area of design and implementation of signal processing systems. It addresses all aspects of architecture and design methods of these systems. Emphasis is on current and future challenges in research and
development in both academia and industry.
Important Dates:
Technical Papers: 03 April 2024
Paper Notifications: 26 June 2024
Special Session Proposals: 31 July 2024
Tutorial Proposals: 31 July 2024
The 37th IEEE Workshop on Signal Processing Systems (SiPS) is a premier international forum in the area of design and implementation of signal processing systems. It addresses all aspects of architecture and design methods of these systems. Emphasis is on current and future challenges in research and
development in both academia and industry.
Important Dates:
Technical Papers: 03 April 2024
Paper Notifications: 26 June 2024
Special Session Proposals: 31 July 2024
Tutorial Proposals: 31 July 2024